Computer including data signal monitoring circuit

ABSTRACT

In a system having a processor, a memory and a peripheral circuit which communicate via a common bus, a signal detector and a compression circuit are included to facilitate data monitoring by a logic simulator. The signal detector is also connected to the common bus. In monitoring a target circuit, the signal detector decodes an address of a bus signal to determine if the signal is input to/output from the target circuit. The signal detector applies mask data, stored in a mask memory, to the bus signal, except for the bus data input to/output from the target signal, to generate a masked signal. The masked signal is then compressed using the compression circuit. The data input to/output from the target circuit and the compressed, masked signal are then stored in a memory of the logic simulator. Masking and compressing the bus signals reduces the amount of data stored by the logic simulator.

BACKGROUND OF THE INVENTION

The present invention relates to a data signal monitoring method andapparatus, and more particularly, to a method and apparatus formonitoring, in a logic simulation, a data signal of a target circuittransmitted on a common bus in a system.

A microcomputer (CPU), a memory and an input/output circuit areconnected to a common bus. The CPU operates according to program datastored in the memory to communicate a data signal including aninstruction between the memory and the peripheral circuit.

A logic simulator is connected to the common bus to monitor whether oneor more circuits operate normally. That is, the simulator monitors thedata signal supplied to or output from a target circuit to check theoperation of the target circuit. The simulator determines whether themonitored data signal matches an expected data signal corresponding tothe operation of the system. Based on the determination result, whetherthe target circuit operates normally is determined.

However, because the system configuration is very complicated, manykinds of data signals are supplied on the common bus. This makes itdifficult to monitor the target circuit data signal and the operation ofthe target circuit.

One method for monitoring a target circuit data signal traces all of thedata signals on the common bus, displays the traced data signals on aCRT or other suitable display tool and separates the data signals tomonitor the target circuit data signal. However, as the systemconfiguration becomes more complicated, the system operation takes alonger time, and simulation for tracing the data signal also takes alonger time. Further, a large capacity memory is needed to trace thedata signals for a long period of time. Therefore, it is disadvantageousin terms of cost and time to monitor the data signals by tracing.

An object of the present invention is to provide a method and apparatuswhich facilitate monitoring a data signal of a target circuit.

SUMMARY OF THE INVENTION

Briefly stated, the present invention provides, in a system having oneor more circuits mutually connected via a common bus, a method formonitoring a data signal input to/output from a target circuit via thecommon bus. The method includes the steps of: receiving informationabout the target circuit; determining, based on the information aboutthe target circuit, whether a data signal supplied on the common bus isthe data signal input to/output from the target circuit; passing thedata signal input to/output from the target circuit based on the resultof the determination; and masking the data signal input to/output fromthe one or more circuits except the target circuit.

The present invention provides an apparatus for monitoring data signalssupplied on a common bus which mutually connects one or more circuits.The apparatus includes a detection circuit and a masking circuit. Thedetection circuit is connected to the common bus. The detection circuitreceives the data signals supplied on the common bus and discriminates afirst data signal input to/output from a target circuit from a seconddata signal input to/output from the other circuits. The masking circuitmasks the second data signal and generates a masked second data signal.

Other aspects and advantages of the invention will become apparent fromthe following description, taken in conjunction with the accompanyingdrawings, illustrating by way of example the principles of theinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention, together with objects and advantages thereof, may best beunderstood by reference to the following description of the presentlypreferred embodiments together with the accompanying drawings in which:

FIG. 1 is a block diagram of a data signal monitoring system accordingto one embodiment of the present invention;

FIG. 2 is a block diagram of a signal detector in the system of FIG. 1;

FIG. 3 is a waveform diagram of data signals output from the signaldetector of FIG. 2;

FIG. 4 is a waveform diagram of data signals output from the signaldetector of FIG. 2;

FIG. 5 is a waveforms diagram of data signals supplied to a compressioncircuit in the system of FIG. 1, a data signal processed in thecompression circuit and a data signal output from the compressioncircuit;

FIG. 6(a) shows data signals stored in a trace memory and correspondingaddresses in a logic simulation which receives the data signal from thesystem of FIG. 1; and

FIG. 6(b) shows a data signal stored in a trace memory and correspondinginformation about an output destination circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

One embodiment of the present invention is described hereinafteraccording to FIGS. 1-6. Referring to FIG. 1, a system 11 comprises a CPU12, such as a microcomputer, a memory 13 and a peripheral circuit 14.The memory 13 preferably includes a program memory and a data memory.The program memory stores control program code including an executeinstruction of the CPU 12 for operating the system 11. The data memorystores initial values necessary to execute the control program andtemporarily stores data during processing (i.e., Program codeexecution). The peripheral circuit 14 includes a predetermined functioncircuit or a function circuit set according to the user'sspecifications, for example, a timer circuit or a counter circuit.

The system 11 includes a common bus 15 which mutually connects the CPU12, the memory 13 and the peripheral circuit 14. The common bus 15includes an address bus 16, a data bus 17 and a control bus 18. Thecommon bus 15 allows the CPU 12, the memory 13 and the peripheralcircuit 14 to communicate with each other by passing both commands anddata to each other.

The CPU 12 inputs/outputs an address signal AD, a data signal DT and acontrol signal CS to/from the memory 13 and the peripheral circuit 14.The address signal AD is transferred on the address bus 16. The datasignal DT is transferred on the data bus 17 and includes a controlinstruction and/or data. The control signal CS is transferred on thecontrol bus 18 and includes an access control signal for the memory 13and the peripheral circuit 14, a read signal, a write signal, a dataacknowledge signal and a data strobe signal. Each bus 16-18 is formedfrom a plurality of signal lines which correspond to a number of bits,as is known to those of ordinary skill in the art.

The CPU 12 provides the address signal AD and the control signal CS tothe memory 13 and the peripheral circuit 14 via the common bus 15 andselects a target circuit to input/output the data signal DT. The CPU 12inputs/outputs the data signal DT to/from the target circuit (the memory13 or the peripheral circuit 14) via the common bus 15.

Specifically, the CPU 12 first sends the address signal AD on theaddress bus 16 to select the memory 13 or peripheral circuit 14. The CPU12 then sends the control signal CS on the control bus 18 to setoperation of the memory 13 or peripheral circuit 14. The CPU 12 finallysends the data signal DT on the data bus 17 to transfer the data signalDT output from the memory 13 or the peripheral circuit 14, of course, aswill be understood by those of ordinary skill in the art, the addresssignal AD, the control signal CS and the data signal DT may be placed onthe respective busses 16-18 substantially simultaneously.

The system 11 further comprises a signal detector 21 as a maskingcircuit and a compression circuit 22 as a signal compressor. A logicsimulator 23 is connected to the common bus 15 via the compressioncircuit 22 and the signal detector 21. The logic simulator 23 simulatesoperation of the system 11. The logic simulator 23 receives the datasignal DT output on the data bus 17 via the signal detector 21 and thecompression circuit 22.

The signal detector 21 masks the data signal DT input to/output fromnon-target circuits among those supplied on the data bus 17 and sendsthe masked data signal DT to the compression circuit 22. Masking of thedata signal DT by the signal detector 21 facilitates monitoring the datasignal DT.

Referring to FIG. 2, the signal detector 21 comprises an address decoder25, a data mask unit 26 and a mask condition setting memory 27. The maskmemory 27 stores information corresponding to the data signal DT inputto/output from the selected target circuit, which is supplied from thelogic simulator 23. That is, the logic simulator 23 sends predeterminedinformation to the signal detector 21 to select the data signal DT inputto/output from the target circuit (the memory 13 or the peripheralcircuit 14) for the purpose of checking the operation of the targetcircuit, of course, even the CPU 12 could be designated as the targetcircuit.

The information includes information about the address signal AD toselect a target circuit, information indicating the state on the databus 17 over which the target data signal DT is transferred (e.g., thelevel of the control signal CS) and information to set a masking level.

The address decoder 25 receives the address signal AD supplied on theaddress bus 16 and decodes the signal AD. The decoded address signal issupplied to the mask unit 26. The mask unit 26 receives each signalsupplied on the busses 16-17, as well as the decoded address signal fromthe address decoder 25. The mask unit 26 further receives the maskinformation stored in the mask memory 27. In this case, the informationincludes address information specifying the target circuit andinformation to indicate the timing to receive the data signal DT (i.e.,the information about the level of the control signal CS).

The mask unit 26 compares the decoded address signal with the addressinformation from the mask memory 27 and determines whether the currentinput data signal DT is the target data signal. Referring to FIGS. 1 and3, the mask unit 26 outputs a masked data signal D1 when the controlsignal CS has a specified level. If the current data signal DT is notthe target data signal, the mask unit 26 outputs the masked data signalD1 having a certain level according to the level information stored inthe mask memory 27. In the present embodiment, the target data signal isoutput when the control signal CS has a low (L) level. Alternatively,the target data signal output condition may be determined by acombination of two or more control signals having predetermined levels.The condition may also be determined by the result of comparing theaddress signal AD with the address information or by the level of thecontrol signal CS.

The level of the masked data signal D1 is high (H) level, low (L) levelor intermediate (Z) level. The mask memory 27 stores informationcorresponding to the signal levels.

Referring to FIG. 4, the mask unit 26 outputs the masked data signal D1ahaving an L level according to the information indicating the L level.The mask unit 26 outputs the masked data signal D1b having an H levelaccording to the information indicating the H level. The mask unit 26further outputs the masked data signal D1c having an intermediate levelbetween the H level and the L level according to the informationindicating the Z level. The data signal D1c having the intermediatelevel is output when the output terminal of the mask unit 26 is in thehigh impedance state. Changing the masked data signal level allows thetarget data signal D1 to be definitely discriminated from the maskeddata signal D1. For example, when the target data signal has an L level,the mask unit 26 outputs the masked data signal D1 having an H level,thereby definitely discriminating the target data signal from the maskeddata signal D1. This facilitates monitoring the target data signal.

Thus, the signals transferred on the bus 15 are input to the signaldetector 21. The address signal AD is input to the address decoder 25 todetermine whether the data on the bus 15 pertains to the selected targetcircuit and is to be considered as a target data signal. The data maskunit 26 receives the bus 15 data, the decoded address, and the maskinformation stored in the mask memory 27 and, if the bus 15 data signalis not directed to/from the target circuit, then the mask is applied tothe bus data signal and the mask data signal D1 is generated.

The masked data signal D1 is input to the compression circuit 22 (FIG.1). Referring to FIG. 5, DT indicates the target data signal on the databus 17. D1 shows the corresponding masked data signal. In FIG. 5, themasked data signal D1 corresponds to the data signal DT in the first andthird cycles and has masked data at the second cycle. The compressioncircuit 22 compresses the masked data signal D1 to generate a compressedmasked data signal D2 by outputting the masked data (i.e. at the secondcycle) only for a predetermined limited time period. In the example, thepredetermined limited time period is shown as t1. After thepredetermined time period t1 has ended, the compression circuit 22 stopsoutputting the masked data portion of the masked data signal D1. Thepredetermined time period t1 is preferably set to a time long enough todiscriminate the next target data signal D1. The compressed masked datasignal D2 is then supplied to the logic simulator 23.

The logic simulator 23 receives the compressed masked data signal D2. Asdiscussed above, the compressed masked data signal D2 includes thedesired target data (indicated as Da in FIG. 5) and the compressedmasked data (which spans the time period t1 in FIG. 5). The logicsimulator 23 stores the compressed masked data signal D2 preferably insequential locations of a trace memory 24 (FIG. 1). By masking the dataon the bus 15 and then compressing the data sent to the logic simulator23 prior to storing such data, the memory size requirements of the tracememory 24 are decreased. Thus, a large amount of desired data can bestored in the trace memory 24. As a result, it is possible to simulateand monitor signal waveforms of a target circuit for a long period oftime.

Referring now to FIGS. 6(a) and 6(b), the compressed data signal D2 ispreferably stored in the trace memory 24 in a location corresponding toits output destination address (FIG. 6(a)), or alternatively, in alocation corresponding to the destination circuit (FIG. 6(b)).

As described above, the data signals input to/output from the circuitsexcept the target circuit are masked, the data signal input to/outputfrom the target circuit is easily identified. By changing properly theinformation about the target circuit stored in the mask memory 27, thedata signal input to/output from a desired target circuit is selectivelyidentified. Further, by changing properly the masking level informationstored in the mask memory 27, the data signal DT input to/output fromthe target circuit is easily discriminated from the masked data signalD1. As the masked data signal D1 is compressed by the compressioncircuit 22, the amount of data supplied to the logic simulator 23 isdecreased, allowing a large amount of desired data to be stored in thetrace memory 24, so that it is possible to simulate and monitor thesignal waveforms for a long time.

It should be apparent to those skilled in the art that the presentinvention may be embodied in many other specific forms without departingfrom the spirit or scope of the invention. Particularly, it should beunderstood that the invention may be embodied in the following forms.For example, instead of the system 11 including the signal detector 21and the compression circuit 22, the logic simulator 23 may have a signaldetector 21 and a compression circuit 22. The system 11 may have asignal detector 21 and the logic simulator may have a compressioncircuit 22. Further, the compression circuit 22 may be omitted dependingon the size of the logic simulator memory 27. Also, it will beunderstood by those of ordinary skill in the art that the common bus 15may include other schemes/protocols for allowing communication betweenthe devices connected to it. Therefore, the present examples andembodiments are to be considered as illustrative and not restrictive andthe invention is not to be limited to the details given herein, but maybe modified within the scope and equivalence of the appended claims.

What is claimed is:
 1. In a system having one or more circuits mutuallyconnected via a common bus, a method for monitoring data signals inputto/output from a target circuit via the common bus, comprising:receivinginformation about the target circuit; determining, based on theinformation about the target circuit, whether a data signal suppled onthe common bus is the data signal input to/output from the targetcircuit; passing the data signal input to/output from the target circuitbased on the result of the determination; and masking the data signalinput to/output from the one or more circuits except the target circuit.2. The method of claim 1, wherein masking the data signal includesgenerating a data signal having a predetermined level to mask the datasignal.
 3. The method of claim 2, further comprising compressing themasked signal having the predetermined level.
 4. The method of claim 3,further comprising storing the compressed masked data signal.
 5. Anapparatus monitoring data signals supplied on a common bus whichmutually connects one or more circuits, comprising:a detection circuit,connected to the common bus, receiving the data signals supplied on thecommon bus and discriminating a first data signal input to/output from atarget circuit from a second data signal input to/output from the othercircuits; and a masking circuit which masks the second data signal andgenerates a masked second data signal.
 6. The apparatus of claim 5,wherein the masking circuit receives information about the targetcircuit and the first data signal and masks the second data signal basedon the information.
 7. The apparatus of claim 6, wherein the informationabout the first data signal includes address information of the targetcircuit, and the detection circuit discriminates the first data signalfrom the second data signal by comparing the address information with anaddress signal supplied on the common bus.
 8. The apparatus of claim 5,wherein the masking circuit masks the second data signal to generate amasked second data signal having a predetermined level.
 9. The apparatusof claim 5, further comprising a memory to store the first and seconddata signals.
 10. The apparatus of claim 5, further comprising:acompression circuit which receives the first data signal and the maskedsecond data signal from the detection circuit and compresses the maskedsecond data signal; and a memory storing the first data signal and thecompressed masked second data signal.
 11. A computer system connectableto a data monitor which monitors a target circuit of the computersystem, comprising:a processor performing arithmetic operations; amemory storing at least one of a program code and data; a peripheralcircuit performing predetermined operations; a common bus connecting theprocessor, the memory and the peripheral circuit and allowing theprocessor, the memory and the peripheral circuit to communicate witheach other; and a signal detection circuit connected to the common busmonitoring bus traffic and detecting the bus traffic input to or outputfrom the target circuit such that when the data monitor is connected tothe computer system by way of the signal detection circuit, the datamonitor only receives the bus traffic input to and output from thetarget circuit.
 12. The computer system of claim 11, wherein the signaldetection circuit includes a compression circuit which compresses thedetected bus traffic to generate a compressed signal and passes thecompressed signal to the data monitor.
 13. The computer system of claim11, wherein the target circuit is one of the memory and the peripheralcircuit.